You are here : Home > WORKSHOPS > D43D'2018 Workshop

editorial content

D43D workshop

Published on 12 June 2018

D43D.png       logo.jpg                             

D43D'2018 Workshop: Steering up design enablement and 3D technologies for the best applications          

The D43D'2018, the 10th Workshop on Design for 3D Silicon Integration, will happen in Minatec on 02-03 July 2018. This year the D43D workshop will be strongly associated with the 3D integration program of IRT Nanoelec.

Following last year successful association with the Leti Memory Workshop (LWM), the D43D workshop will share this year the technical program with the Leti Memory Workshop, and the Leti Photonic Workshop. 

 Workshop Content                                    

3D IC is emerging as a promising approach to extend Moore’s law, overcome pin bandwidth limitations, and improve digital platform density and cost beyond a single chip. 3D IC as a technology, however, also introduces a number of key design, methodological, implementation and technological challenges that must be overcome to make them practical and cost-effective. As of today, 3D technology is getting more and more mature with 3D memory cubes, imagers, large size passive interposers. Nevertheless, new 3D technologies are appearing, with 3D memory devices, 3D High Density technologies, the co-integration with photonic devices as well as 3D sequential technologies, opening a wild scope of new application spectrum, but also its new technical challenges.

The D43D workshop is a two-day forum that brings together experts from both industry and academia to shed light on these near-term to long-term challenges and solutions and covers topics including, but not limited to : 3D technology, including the recent upcoming 3D sequential technology (CoolCubeTM), co-integration of 3D technology and recent 3D memory NVM devices, 3D architecture for Computing, interconnect architectures, thermal management, 3D for photonic, 3D for imager applications, design methodologies and tools, reliability and testing. The objective is to bring experts from both the industry and the academia to share recent results on the latest and most advanced 3D technologies.

 Workshop Technical Program Overview

orkshop Technical Program

13:00 - 14:30 Welcome Lunch  

14:30 - 14:35Opening SessionPascal Vivet, CEA-LETI, France
SESSION 1        Advanced 3D Image Sensors with Smart Features
                           Chairman: Gilles Sicard, CEA-Leti, France
14:35 - 15:00Direct Time-of-Flight (dTOF) imaging for depth sensing applications Augusto Ronchini Ximenes, TU Delft, Nederlands
15:00 - 15:303D Architecture of a Fast Digital Burst Video SensorWilfried Uhring, ICUBE Laboratory, Univ. Strasbourg, France
15:30 - 16:00RETINE: a 3D stacked in-focal-plane vision chip for monitoring applications Laurent Millet, CEA-Leti, France
16:00 - 16:30 Coffee Break
SESSION 2      3D Integration Challenges for Photonics communication,  
                          Chairman: Alexis Farcy, STMicroelectronics, France
16:30 - 16:50
System-level Optimizations for 2.5D-integrated Chips with Silicon-Photonic LinksAyse Coskun, Univ. of Boston, USA
16:50 - 17:10Toward a Top-Down Synthesis Methodology for 3D-Stacked Wavelength-Routed Optical NoCsDavide Bertozzi, Univ. of Ferrara, Italy
17:10 - 17:30TBDIan O'Connor, INL, France
17:30 - 17:50Face-to-face integration of an electro-optical link with CMOS drivers and thermal controlYvain Thonnart, CEA-Leti, France
18:00End of D43D day 1

TUESDAY, JULY 3rd  2018
8:30 - 9:00 Welcome Coffee  
SESSION 3      3D Systems for Machine Learning and Memory architecture
                          Chairman: Subhasish Mitra, Stanford Univ., USA
9:00 - 9:30
3D Systems for Machine LearningPaul Franzon, Univ. of North Carolina, USA
9:30 - 10:00NTX: A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory DatasetsLuca Benini, Univ. Bologna, Italy and ETH Zurich, Switzerland
10:00 - 10:30Challenges of 3D DRAM MemoriesChristian Weis, Univ. of Kaiserslautern, Germany
10:30 - 11:15 Coffee Break
SESSION 4     3D Technology: Keynote and Panel 
                        Chairman: Severine Cheramy, CEA-LETI, Grenoble, France
11:00 - 11:45​

3D scalability from high performance to ultra low power

Marcel Wieland, Global Foundry, Germany
11:45 - 12:15

Anton Korzh, Micron, USA

12:15 - 13:00Panel "3D Technology : which road for which disruptive architectures ?"

Panelists :
- Subhasish Mitra, Univ. Stanford, USA
- Paul Franzon, NCSU, USA
- Marcel Wieland, Global Foundry, Germany,
- Francois Jacquet, KALRAY, France,
- Denis Dutoit, CEA-LETI, France

13:00 - 14:30 Lunch Break
SESSION 5      Monolithic 3D and advanced signalling,  
                         Chairman: Laurent Le-Pailleur, STMicroelectronics, France
14:30 - 15:003D sequential integration : review of opportunities and technology updatesPerrine Batude, CEA-Leti, France
15:00 - 15:30   3D sequential integration : overview of 65 nm on 28 nm FDSOI MPW architecture and design contributions Sébastien Thuriès, CEA-Leti, France
15:30 - 16:00Wireline Communication in 2.5-D and 3-D ICsPrzemyslaw Mroszczyk, Univ. Manchester, UK

16:00 - 16:30 Coffee Break

SESSION 6     3D Advanced Packaging and CAD tools
                        Chairman: Pascal Vivet, CEA-LETI, France
16:30 - 16:55Solutions for high density advanced package design and verificationPascal Leclaire, Mentor Graphics, France
16:55 - 17:20
From 2.5D to 3D layout design environment: Status and future challenges for advanced 3D packagingThomas Brandtner, INFINEON, Austria
17:20 - 17:45CAD Flow methodologies for 3D Hybrid sub-systemsLise Doyen, STMicroelectronics, France
17:45 Closing Remarks, End of day 2


  • ​​D43D workshop: € 300

  • Registration includes 

        - Lunch 
        - Morning and afternoon coffee breaks 
  • Register for D43D workshop                                  

More info