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Design for 3D Stacking

Published on 12 June 2019



D43D 2019 - Design for 3D Stacking Workshop
Tuesday, June 25th 2019



Coupling Design Performance and 3D Technologies  



Leti Design for 3D Stacking is a one full-day Workshop that brings together experts from both industry and academia to shed light on near-term to long-term challenges. Experts will cover the latest available results in:

  • 3D sequential technology & 3D memory NVM devices
  • Co-integration of 3D Technology
  • 3D architecture for computing, interconnects architectures, thermal management
  • 3D for photonics and imager applications
  • Design methodologies and tools, reliability and testing


For who?

  • Industrials
  • Designers
  • 3D experts


Program

08:30    Registration & Welcome coffee
HPC SESSION
​09:00
Chiplet-Based Partitioning Using Smart Interposer for High Performance Computing 3D Integrated Systems
  • CEA-Leti, Fabien Clermidy
​09:30
​Package Architecture Optimization for High Performance Computing
  • Intel, Shawna Liff
10:00
Requirements for Advanced Co-Packaged Silicon Photonics
  • HPE, Ashkan Seyedi
10:30    Coffee Break & Networking
3D IMAGER SESSION
11:00
Advanced 3D Technologies and Architectures for 3D Smart Image Sensors
  • CEA-Leti, Pascal Vivet
11:30
​3D Integration Benefits for Intelligent Image Sensors
  • Prophesee, Jean-Luc Jaffard
​12:00
​A Camera with Brain - Embedding Machine Learning in 3D Sensors
  • Georgia Institute of Technology, Prof. Saibal Mukhopadhyay
12:30​    Buffet Lunch & Networking
14:00
From Technology to Market, Stacking Is Becoming Necessary in Multiple Markets & Applications
  • Yole Development, Mario Ibrahim
TECHNOLOGY ENABLER FOR ADVANCED 3D
14:30
​Advanced 3DIC Technologies
  • CEA-Leti, Séverine Cheramy
​15:00
Die to Wafer Hybrid Bonding Equipment From R&D to Production
  • SET, Nicolas Raynaud
15:30
​New Cu and Co Metallization Enabling Multiple Integrations
  • Aveni, Celine Doussot
16:00​    Coffee Break & Networking
HETEROGENEOUS 3D APPLICATIONS
16:30
3D Landscape for the Post-Moore Transition
  • Huawei, Xiang Xu 
​17:00
Designing Heterogeneous Chips with zGlue
  • Zglue, Jawad Nasrullah
18:00    End

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